1. Field of the Invention
The present invention relates, in general, to computer architecture and more particularly, to a computer architecture having an enhanced peripheral component interconnect (PCI) bus providing multiple speed data transfers using a single clock and having split transaction capability.
2. Statement of the Problem
Computer systems demand increasingly higher data transfer rates. For example, graphics oriented operating systems such as Windows and OS/2 require large amounts of data to be transferred between the central processing unit (CPU) and the devices that drive display devices such as a monitor. Even though CPU clock speeds have increased, conventional data bus architectures have created a data bottleneck between the CPU and these data intensive peripheral devices.
In conventional personal computer (PC) architectures, the CPU, main memory, and other peripheral input/output (I/O) devices are commonly coupled by a bus network having a local bus and a system bus. The system bus connects to the local bus and is generally slower than the local bus. Examples of common system bus architectures are the industry standard architecture (ISA), extended industry standard architecture (EISA) and the micro channel (MC) bus. The dual bus network evolved in part because early PCs required high speed data transfer only between the CPU and the main memory. Consequently, the CPU and the main memory are situated in the faster local bus, while the video subsystem as well as other peripheral I/O devices with varying clock speeds are usually connected to the slower system bus.
PCs have evolved to the point where high-speed data transfer is a critical factor in overall performance of the system. In particular, graphics intensive applications such as Computer Aided Design (CAD) require high-speed video devices that can drive high-resolution displays with more colors and three-dimensional capabilities. Video systems are being developed that require far more data transfer capability that current bus architectures and protocols can support.
Two bus architectures are currently available that allow high-speed devices to couple to the local bus to provide high data transfer rates between devices on the bus. The Video Electronics Standards Association (VESA) established a standard local bus that allowed some components, such as graphics cards, to interface directly with the local bus. In the VESA bus, the bus clock speed is controlled by the CPU clock speed. The Peripheral Component Interconnect (PCI) bus offers another architecture in which a bus controller sits between the CPU local bus and a device such as a graphics card. According to the PCI specification, a master device coupled to the PCI bus requests a data transaction with a specific target device, also coupled to the PCI bus. Both the master and target devices conduct the data transaction according to the PCI specified protocols. The PCI bus is not tied to the speed of the CPU, however, the PCI specification limits bus clock speed to 33 megahertz (MHz). In either the VESA bus or the PCI bus, data transfer occurs at most only once per clock cycle, thus the bus data transfer rate is limited to the bus clock speed, thereby limiting devices that are capable of and demand higher data transfer rates.
Another problem with the PCI bus architecture is that data transfers must occur immediately after a request is made. Often times a slow target device is unable to respond immediately. In accordance with the PCI bus specification, the bus is locked until the transaction between the master device and the slow target device is completed. Hence, the bus cannot support other data transactions until the slow device has responded. This slows overall speed and performance of the PC. A need exists in the PCI bus architecture for allowing data transactions to continue while a slow device prepares requested data.
Bus design and protocol is strictly regulated by industry standard specifications that dictate physical, mechanical, and electrical requirements for the bus. These specifications are necessary to ensure that devices from a wide variety of manufacturers can use the bus without negatively impacting other devices using the bus. One problem with industry standard specifications is that improvements to the bus architecture or protocol are difficult to implement. Hence, it is necessary that improvements to the protocol are compatible with existing protocol and devices that comply with the industry standard specification.
3. Solution to the Problem
The above identified problems are solved by a PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data at higher data rates than the bus clock speed. By transferring data more than once per clock cycle, the data transfer rate is multiplied. Another feature of the present invention is a protocol allowing a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.